1. Field of the Disclosure
The present disclosure relates to polishing compositions, and methods for polishing semiconductor substrates using the same. More particularly, this disclosure relates to polishing compositions and methods for polishing cobalt films with various rates and selectivities in semiconductor substrates containing multiple dielectric and metal films.
2. Description of the Related Art
The semiconductor industry is continually driven to improve chip performance by further miniaturization of devices by process, materials, and integration innovations. Earlier materials innovations included the introduction of copper, replacing aluminum as the conductive material in the interconnect structure, and the use of tantalum (Ta) (adhesion)/tantalum nitride (TaN) (barrier) to separate the Cu conductive material from the non-conductive/insulator dielectric material. Copper (Cu) was chosen as the interconnect material because of its low resistivity and superior resistance against electro-migration. However, as the features of the chip shrink, these multilayer Cu/barrier/dielectric stacks have to be thinner and more conformal to maintain effective interconnect resistivity in Back End of Line (BEOL). However, Cu and the Ta/TaN barrier film scheme present problems with resistivity and flexibility in deposition. With smaller dimensions and advanced manufacturing nodes, resistivity is getting so much exponentially worse that improvements in transistor circuit speed (at Front End of Line (FEOL)) are being cut in half by the delay coming from the conductive Cu/Barrier wiring (BEOL). Cobalt (Co) has emerged as a leading candidate for both the barrier layer as well as the conductive layer. Furthermore, cobalt is also being investigated as a replacement for tungsten (W) metal in multiple applications such as W metal contacts, plugs, vias, and gate materials.
Chemical Mechanical Polishing/Planarization (CMP) is a semiconductor fabrication process technology that is used to polish and planarize metals and dielectrics in BEOL and FEOL. For instance, for Cu CMP, the conductive Cu layer is polished and planarized until either the barrier layer or the insulator dielectric layer is exposed. The CMP process is performed by using a polishing composition (slurry) on a polishing tool that holds the wafers and presses it against a polishing pad. The concomitant application of chemistry (slurry) and mechanical forces (pressure) causes “Chemical Mechanical” polishing of the wafers. The end goal of the CMP step is to achieve local and global planarity post polishing along with a defect-free and corrosion-free surface. Some key metrics of the CMP slurry/process are Material Removal Rates (MRRs), surface defectivity post-polishing, and metal corrosion/etching prevention post-polishing.
With the introduction of Cobalt (Co) as a barrier layer, conductive layer, and/or W replacement, there is a market need for Co CMP slurries that can polish Co at high MRRs and have a range of selectivities in polishing rates of other metals and metal oxides (Cu, Ti, Ta2O5, TiO2, RuO2, etc.), and dielectric films (SiN, Silicon Oxide, P—Si, low k dielectrics, etc.). Because Co is more chemically reactive than Cu and other noble metals, Co corrosion prevention is very challenging in advanced nodes' slurry design. Current metal polishing slurries are ill-equipped to polish Co films as they suffer from Co corrosion issues in the CMP process. Thus, it is highly desirable to have Co slurries that can remove Co films while not causing Co corrosion.
FIGS. 1a and 1b display two Back End stack applications, as examples, in which Co slurries are needed. Each shows both a Co Bulk slurry (Co conductive layer), and a Co Barrier slurry (Co barrier layer). The application in FIG. 1a uses an additional metal oxide layer not needed for the application of FIG. 1b. 